1. Technical Field
Various embodiments generally relate to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus.
2. Related Art
A semiconductor memory apparatus is configured to store data and output stored data. According to methods of storing inputted data, semiconductor memory apparatuses are classified into various kinds.
Research has been conducted for a semiconductor memory apparatus which is configured to store data by changing the resistance value of a memory cell according to the data value of inputted data and output stored data by discriminating the resistance value of the memory cell.
Referring to FIG. 1, such a semiconductor memory apparatus includes a column address decoding unit 10, a row address decoding unit 20, a driving driver unit 30, first to fourth resistive memory elements 41 to 44, first to fourth current sink units 51 to 54, and a read write circuit unit 60.
The semiconductor memory apparatus configured in this way operates as follows.
The column address decoding unit 10 decodes a column address Y_add and enables a column select signal C_s.
The row address decoding unit 20 decodes a row address X_add, and generates first to fourth word line select signals WL_s<0:3>. Only one of the first to fourth word line select signals WL_s<0:3> is enabled at a time.
The driving driver unit 30 includes a driving driver P1 and provides a driving voltage V_dr or driving current I_dr to the first to fourth resistive memory elements 41 to 44 in response to the column select signal C_s.
The first current sink unit 51 includes a first transistor N1. The first transistor N1 has a gate which is applied with the first word line select signal WL_s<0>, a drain to which the first resistive memory element 41 is electrically coupled, and a source to which the ground terminal VSS is electrically coupled. As such, the first current sink unit 51 flows current from the first resistive memory element 41 to a ground terminal VSS in response to the first word line select signal WL_s<0>.
The second current sink unit 52 includes a second transistor N2. The second transistor N2 has a gate which is applied with the second word line select signal WL_s<1>, a drain to which the second resistive memory element 42 is electrically coupled, and a source to which the ground terminal VSS is electrically coupled. As such, the second current sink unit 52 flows current from the second resistive memory element 42 to the ground terminal VSS in response to the second word line select signal WL_s<1>.
The third current sink unit 53 includes a third transistor N3. The third transistor N3 has a gate which is applied with the third word line select signal WL_s<2>, a drain to which the third resistive memory element 43 is electrically coupled, and a source to which the ground terminal VSS is electrically coupled. As such, the third current sink unit 53 flows current from the third resistive memory element 43 to the ground terminal VSS in response to the third word line select signal WL_s<2>.
The fourth current sink unit 54 includes a fourth transistor N4. The fourth transistor N4 has a gate which is applied with the fourth word line select signal WL_s<3>, a drain to which the fourth resistive memory element 44 is electrically coupled, and a source to which the ground terminal VSS is electrically coupled. As such, the fourth current sink unit 54 flows current from the fourth resistive memory element 44 to the ground terminal VSS in response to the fourth word line select signal WL_s<3>.
The read write circuit unit 60 performs read operations by being provided with current or voltages from the resistive memory elements 41 to 44 selected by the first to fourth word line select signals WL_s<0:3> and the column select signal C_s, and performs write operations by providing current or voltages to the selected resistive memory elements 41 to 44. Selected resistive memory elements refer to resistive memory elements through which current may flow, among the first to fourth resistive memory elements 41 to 44, in response to the column select signal C_s and the first to fourth word line select signals WL_s<0:3>.
As shown in FIG. 1, the conventional semiconductor memory apparatus is configured such that the plurality of resistive memory elements 41 to 44 are provided with current or voltages from the one driving driver unit 30. Therefore, the resistive memory element 41 closest to the driving driver unit 30 is provided with a largest amount of current or a highest voltage, and the resistive memory element 44 farthest from the driving driver unit 30 is provided with a smallest amount of current or a lowest voltage. That is to say, since the distances between the driving driver unit 30 and the first to fourth respective resistive memory elements 41 to 44 are different, the respective resistive memory elements 41 to 44 are provided with different amounts of current or different levels of voltages. As a result, when sensing (reading) the resistance values of the first to fourth resistive memory elements 41 to 44 or changing (writing) the resistance values of the first to fourth resistive memory elements 41 to 44, it may be difficult to normally perform the read and write operations, due to such a problem.